1. Field of the Invention
The present invention relates to storage circuitry and a method of operation of such storage circuitry, which provides increased resilience to single event upsets.
2. Description of the Prior Art
Storage elements in data processing systems are susceptible to single event upsets (SEUs), such an SEU causing a change of state in the stored data due to ions or electro-magnetic radiation striking a sensitive node within the device and causing the state to flip. Many different approaches have been proposed in the prior art literature to seek to achieve SEU robustness in storage cells.
For example, one known prior art technique is referred to as built-in soft error resilience (BISER). In accordance with a BISER technique, a data signal is sampled using two conventional master-slave flip-flops, and the output of the two flip-flops are then passed through a C-element. The C-element will only allow a data value to propagate from its output if the output of the two flip-flops match. Since an SEU will only typically affect one of the flip-flops, this ensures that the output propagated from the C-element does not change in the presence of an SEU. Such BISER techniques are described for example in the article by Zhang, M., Mitra, S., Mak, T. M., Seifert, N., Wang, N. J., Shi, Q., Kim, K. S., Shanbhag, N. R., and Patel, S. J., entitled “Sequential element design with built-in soft error resilience”, IEEE Trans. Very Large Scale Integration Systems, Volume 4, Issue 12 (December 2006), pages 1368-1378, and the article by Ming Zhang, T. M. Mak, Jim Tschanz, Kee Sup Kim, Norbert Seifert, and Davia Lu, entitled “Design for Resilience to Soft Errors and Variations,” IEEE International On-Line Testing Symposium, pages 23-28, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007.
Another technique which also uses C-elements is referred to as radiation hardened by design (RHBD). An RHBD latch design uses three C-elements, an example of such a design being described in the article by Huang, Z. and Liang, H, entitled “A New Radiation Hardened by Design Latch for Ultra-Deep-Sub-Micron Technologies”, Proceedings 14th IEEE International On-Line Testing Symposium, IOLTS, IEEE Computer Society, Washington, D.C., pages 175-176.
Another known prior art technique involves providing functional circuitry within a data processing apparatus with error correction circuitry that is able to detect errors in operation of the functional circuitry and repair those errors in operation. Such an error correction circuit can be embodied in a variety of ways, but in one embodiment may take the form of a single event upset (SEU) tolerant flip-flop such as discussed in commonly owned U.S. Pat. No. 7,278,080, the entire contents of which are hereby incorporated by reference, this patent describing a design technique sometimes referred to as “Razor”. In accordance with the basic Razor technique, errors are detected in the processing stages by comparison of a non-delayed data value with a delayed data value, these data values being captured at slightly different times. Whilst the primary use of the Razor technique is to provide delay-error tolerant flip-flops on critical paths to allow the supply voltage to be scaled to the point of first failure (PoFF) of a die for a given frequency (thus reducing unnecessary margin in a design), it will be appreciated that such a technique also allows SEUs to be detected and corrected in situ. A further paper that describes the Razor technique is “Razor II: In-Situ Error Detection and Correction for PVT and SER Tolerance”, IEEE Journal of Solid-State Circuits (JSSC), Volume 44, No. 1, January 2009.
In accordance with another known design referred to as XSEUFF, redundancy available in scan flip-flops is used, and a majority voting circuit is used to correct errors due to SEUs. Although re-using scan flip-flops saves area, dynamic power overhead is high due to switching activity in the scan flip-flops. Such a technique is described in the article by Jagirdar, A., Oliveira, R., and Chakraborty, T. J., entitled “A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits”, Proceedings of the 21st international Conference on VLSI Design, Jan. 4-8, 2008, pages 39-44.
Commonly owned U.S. patent application Ser. No. 12/285,517, the entire contents of which are hereby incorporated by reference, describes a self-correcting flip-flop design where two extra latches are added, and majority voting is performed to mask a soft error. Such a self-correcting flip-flop increases power overhead, and also increases the clock-Q latency of a conventional master-slave flip-flop.
Another known prior art technique is referred to as a dual interlocked storage cell (DICE). A DICE cell has a number of interlocked P and N transistors which are arranged in such a manner that if a single event upset affects a single node, the remaining transistors within the design will cause the affected node to self-correct. Hence, in accordance with the DICE technique, a number of redundant nodes are provided in order to improve robustness to SEUs. However, each storage element in accordance with such a technique is relatively large and has high power consumption and a significant delay overhead when compared to a conventional master-slave flip-flop. DICE-style cells are described in a number of articles, for example the article by T. Calin, M. Nicolaidis, and R. Velazco, entitled “Upset hardened memory design for submicron CMOS technology”, IEEE Transactions on Nuclear Science, Vol. 43, No. 6, pages 2874-2878, 1996, the article by R. Naseer, and J. Draper, entitled “DF-DICE: a scalable solution for soft error tolerant circuit design”, Proceedings of the International Symposium on Circuits and Systems, May 2006, pages 3890-3893, and the article by Li, Y., S. Yue, Y. Zhao, and G. Liang, entitled “Low power dissipation SEU-hardened CMOS latch,” PIERS Online, Vol. 3, page 1080, 2007.
From the above discussion of known prior art techniques, it will be appreciated that most of these approaches add one or more extra sequential elements (either another master-slave flip-flop or an extra latch) in order to detect an error due to a single event upset, thereby giving rise to an increase in area and power consumption. Further, in accordance with such techniques, error correction is achieved either by using a rollback or instruction replay technique, or by adding glue logic to the sequential element (such as the earlier described C-element), which further increases power overhead and the clock-Q delay.
Accordingly, it would be desirable to provide an improved technique for providing resilience to single event upsets within a storage circuit.